This invention relates to a semiconductor memory device such as a dynamic random access memory (DRAM), and more particularly to a method which can reduce the test time of high-density, highly integrated memory devices, and a circuit which can test the memory devices.
Memory devices integrated by the semiconductor manufacturing processes require various precise processes in proportion to the increase of integration density of the memory devices. Thus, when such processes are performed, dust or contaminants must be avoided. But, as the density of the memory devices increases, the fault ratio of bad to good devices also increases. Accordingly, the memory devices have a built-in RAM test circuit to test internally the RAM. Even if the RAM test is internally carried out, however, the test time becomes longer in proportion to the integration density.
That is, in the conventional RAM test, the RAM test is carried out by a bit unit (2,.times. 4,.times.8,.times.16) using test signals. The time spent for testing increases in accordance with the integration density/xbit. Accordingly, the more integration density increases, the more test time increases, since the writing and reading of data operations are performed by a xbit unit through input/output lines and the written and read data is compared with each other to check for errors.